Integrated paralleling of NPC inverters with suppressed circulating current for high-power renewable energy conversion☆

0 Introduction

Offshore wind power,medium-voltage industrial drives,and other applications require high-power converters.The offshore wind power capacity is steadily increasing to decrease the levelized cost of electricity and enhance power generation efficiency.Currently, the leading products in this sector are approaching a capacity of 14 MW [1,2].Because the voltage level of power electronic equipment cannot be very high,a medium-voltage inverter is not only expensive,but also limited by the voltage level,and cannot be widely used in high-power equipment.Therefore, it is desirable to operate low-voltage inverters in parallel.Owing to its low current harmonics and smaller voltage stress on power electronic devices, a three-level inverter is highly advantageous for high-power applications [3-5].

In addition to increasing the system capacity by paralleling, several studies have been conducted to simultaneously increase the output voltage and reduce current harmonics.The main attempts include interleaved and integrated paralleling(including space vector-based modulation and its equivalent carrier-based implementation).Interleaved paralleling has been widely in single-phase topologies, and can also be applied to three-phase topologies[6,7].By contrast,integrated paralleling treats parallel converters as a multi-level system that can realize a smaller output harmonic distortion than the interleaved method[8-10].

However, zero-sequence current loops occur when the converter operates in parallel.Because the current-loop impedance is extremely small, a small excitation voltage can cause a large circulating current when there are inconsistencies in the hardware parameters,control parameters,or output voltages between the parallel modules.The presence of a circulating current can result in waveform distortion, decreased system efficiency, increased device stress and internal loss, and potential damage to switching devices [11-13].Therefore, the circulating current must be well-controlled to ensure that the parallel converter system can operate normally.

Methods for suppressing the circulating current in parallel converters can be broadly classified into two categories: hardware approaches and modulation techniques.

The hardware method is well-suited for different operation modes.Coupled inductors[14],common mode inductors [15], differential and common-mode integrated inductors [16], or filters [17] can be applied to reduce the magnitude of the loop current.However, the main disadvantage of this hardware method is that the added hardware devices (mostly passive) are typically large and expensive.Significant design and production time must be invested to maintain the complexity of the system;therefore, the volume and value of the system increases[18,19].

Unlike the hardware approach,the modulation method does not require additional hardware components.However,its drawback lies in the requirement of customization to develop appropriate modulation strategies.

In interleaved paralleling, the circulating current is primarily a high-frequency component caused by the carrier difference, which cannot be suppressed or eliminated by adjusting the zero-sequence component.In[20],a suppression method based on selective harmonic elimination pulse-width modulation (PWM) was proposed, which can effectively reduce the loop current amplitude and low-order ripples;however,the calculation process is complicated.Reference [21] combined carrier phase shifting with interleaved parallelism and proposed a two-degreeof-freedom interleaved paralleling algorithm that can significantly reduce the high-frequency circulating current amplitude and can be easily generalized to multimodule parallel inverters.Other related studies have mainly focused on the mechanism of loop current generation,spectrum analysis, and the design of suitable hardware parameters for circulating current suppression.In [22],the effects of different modulation methods, such as phase disposition, phase opposition disposition, and alternative phase opposition disposition, on current quality were investigated.Different modulation methods such as current quality enhancement, common-mode voltage cancellation, and loop current suppression have been characterized.In contrast,[23]focuses on the effect of various interleaved parallel methods on the current harmonic behavior.

In the field of integrated modulation, the concept and execution strategy for parallel three-level inverters, as introduced in [9], leverage the system’s multi-level output capacity.This approach was designed to reduce the output harmonics and minimize the circulating currents, thereby surpassing the performance of traditional interleaving techniques.In [24], an improved virtual space vector PWM strategy that simultaneously solves the common mode voltage and neutral point voltage fluctuation problems in wind turbine converters was proposed.Reference[25] introduces an innovative feedback control approach aimed at balancing the neutral point potential voltage.To quantify the severity of the loss of balance at the neutral potential, the degree can be expressed by setting a coefficient.Reference [26] presented an additive levelbased control method that employs regular modulation to produce AC side voltage levels and developed a model predictive control algorithm designed to alleviate the computational load,thereby facilitating the generation of additional levels to enhance the properties of the DC bus current.Based on the integrated modulation process, discontinuous PWM and zero-common-mode voltage modulation methods have been proposed in [27] and [28],expanding the application area of integrated paralleling.In practice, integrated modulation allocates switching states as additional degrees of freedom, a potential that has not been fully exploited in the aforementioned studies.To further improve and reduce the circulating current,the basic idea of a novel switching sequence design was first proposed in [29].Nevertheless, the correlation between the switching sequence design and loop current has not been thoroughly studied, and experimental verification is lacking.Consequently, as an advanced iteration of [29],this study introduces a new design methodology for switching sequences that features a thorough analysis and verification results grounded in the fundamental concept of integrated modulation.First, it reduces the harmonics of the converter’s output current.Secondly, it can significantly reduce the magnitude of the loop current,thereby offering a more effective solution for high-power inverters.

In addition to hardware and modulation methods, a dedicated control loop is effective in suppressing circulating currents.To suppress the circulating resonance current caused by the LCL filter, a stable control method with a multisampling mode was introduced in [30].Based on the frequency analysis and nonlinear characteristics of the circulating current, a nonlinear disturbance observer and feedback-feedforward control method were adopted in [31] to improve the circulating current suppression performance.In addition, model-free and multivector model predictive control methods were adopted to eliminate the circulating current of the parallel three-level inverters[32,33].However,all control methods require an elaborate design and complicated implementation processes.

To clearly present the characteristics of related works discussed above, the advantages and disadvantages of the methods in terms of the circulating current suppression effect, material cost, implementation complexity, and flexibility are compared and summarized in Table 1.

Section II outlines the design criteria for conventional switching sequences in three-level inverters as well as the basic concept of interleaved paralleling.In Section III,we introduce an enhanced switching sequence for integrated paralleling, which includes a comprehensive implementation process and an analysis of the circulating current.The validity of the proposed methodology is demonstrated through simulations and experiments in Section IV.These results underscore its superiority to traditional switching sequences and interleaved paralleling techniques.Finally, the findings are summarized in Section V.

The primary innovative contributions of this paper encompass the following aspects:

(1) The state-distribution redundancy in the integrated modulation process of parallel three-level inverters was discovered and utilized to formulate a novel switching sequence that provides flexibility and new freedom to the switching sequence design.

(2) A switching sequence with a small circulating current was selected from the available five-level space vectors, reducing the instantaneous circulating current between the parallel inverters.In comparison, the circulating current amplitude was significantly reduced using the proposed method.

(3) Compared with interleaved paralleling and integrated paralleling with a conventional switching sequence, the proposed method can simultaneously achieve superior output current quality and reduced circulating current.

1 Integrated paralleling of three-level inverters

In high-power applications, it is common practice to connect power devices or modules in series to increase the voltage level, as exemplified by multi-level converters with cascaded H-bridge topologies.

A schematic of a parallel three-level converter system employing integrated modulation and vector-oriented control is presented in Fig.1.In this configuration, two parallel-operating three-level converters can be used as a five-level system.

For any three-level converter,each bridge arm can produce three distinct voltage levels corresponding to three switching states.Consequently, the output voltage of the x-phase bridge arm can be expressed as

where V x1N and V x2N are the bridge output voltages of Inverters 1 and 2, respectively, Sx1 and Sx2 are the corresponding switching states of the bridge arms.

Based on the output voltage of the parallel bridge arms,the AC-side voltage of the parallel three-level converter system can be calculated as follows:

From Eq.(2),it is evident that because each three-level bridge arm can output three switching states, the parallel arms have five distinct combinations, thereby enabling the output of five voltage levels.Consequently, by reconstructing the topology of the power devices, the two parallel-operating three-level inverters can be regarded as a single five-level inverter during operation.

The space vector diagram of a five-level inverter is depicted in Fig.2, which illustrates the vector distribution and region division for sector I in detail.The calculation processes for sectors II-VI are analogous to those of sector I, with the only distinction being the difference in the angle, which will not be discussed further here.

In the vector space shown in Fig.2, each sector comprises 16 sub-regions, with small triangular areas representing each sub-region.The vertices of each sub-region are referred to as basic vectors, and except for the outer-most vectors, the remaining vectors have multiple redundant switching states.For integrated modulation,it is necessary to decompose each switching state into parallel three-level inverters, thus requiring a special design to ensure that the distribution of the parallel bridge states contributes to an increase in the output current quality and a reduction in the circulating current.In the parallel operation of the three-level inverters, the overall system state can achieve a five-level output, which means that the output state of the parallel system meets the requirements of the five-level vector space, thereby ensuring that the output harmonics are lower than those of the traditional interleaved parallel method.In addition, when assigning the five-level state to the three-level inverters,attention must be paid to the fact that the state difference should not generate a significant average circulating current to ensure that the entire system operates normally.

Table 1 Comparison of existing works.

Circulating Current Suppression Methods Suppression effectCostComplexityFlexibility Additional Hardware [14-19]HighHighHighLow Interleaved Paralleling [20-23]LowLowLowMedium Integrated Paralleling [24-29]MediumLowMediumHigh

Fig.1 System diagram for integrated paralleling of three-level inverters.

Fig.2 Five-level vector space with sector I.

To prevent the persistent deviation of the circulating currents,the switching sequence of the integrated modulation must be meticulously designed.The fundamental principles primarily encompass the following two aspects of the switching sequence design process.First, the circulating current resulting from the difference in switching states within each switching period must be consistent at the beginning and end of the period.Second, the direction of the average circulating current must be opposite in the preceding and following switching periods, thereby ensuring that the average value of the circulating current over two consecutive switching periods is zero.

For a specific phase, the differential circulating current between the parallel bridge arms can be defined as

For parallel-connected three-level inverters, the circulating current between the inverters can be expressed as:

where L1 and L2 represent the filter inductances at the AC output sides of the parallel inverters.

By substituting the output voltage of the three-level inverter into the equation, it can be further derived as

Because the inductance and DC bus voltage are constant, the rate of change in the circulating current is primarily influenced by the state difference between the parallel-connected bridge arms.

Based on the circulating current shown in Eq.(5), the zero-sequence circulating current is derived as

Based on Eqs.(5)and(6),the zero-sequence circulating current can be expressed as follows:

The rate of change of the circulating current is directly influenced by the state difference between the parallelconnected bridge arms because this difference has a significant effect on the dynamics of the circulating current within the system.Therefore, when allocating five-level states to three-level inverters, it is crucial to minimize the difference in the states between the three-level bridge arms.

Considering sub-region 2 within sector I, the switching sequence for the five-level space-vector modulation was 211-311-321-322-321-331-211.According to the aforementioned design principles, the switching states allocated to the parallel three-level inverters are shown in Fig.3.

2 Proposed switching sequence

Analysis of the state distribution pattern shown in Fig.3 reveals that this sequence ensures a zero-average circulating current.However, the design of the switching sequence does not fully exploit the diversity of state redundancy.For instance, within the first switching cycle, all five-level states of 3 are allocated as the three-level states 1 and 2.This design approach can result in deviations in the circulating current in one direction,thereby generating a significant zero-sequence circulating current throughout the modulation period.

Fig.3 State assignment and circulating current diagram for sub-region 2 within sector I.

The odd-valued five-level states affect the circulating current.For example, using the traditional state distribution pattern shown in Fig.3, the five-level vector 211 is allocated as three-level vectors 111 and 100.However, if the state allocation is conducted according to the novel switching sequence proposed in this paper,such as allocating 211 as 110 and 101, the sum of the state differences is zero, thereby effectively suppressing the circulating current.Corresponding to the state-distribution pattern shown in Fig.3, a diagram of the novel design is shown in Fig.4.When the novel switching sequence was adopted,the circulating current was significantly reduced compared to that of the original switching sequence design.In addition, the harmonic content of the output current of the entire system was not adversely affected because the fivelevel states were identical.

As an additional example, when the reference voltage vector is located within the 9th sub-region of sector I,the traditional and novel switching sequences and their corresponding circulating current trends are shown in Fig.5.It is evident that the proposed novel switching sequence design significantly reduces the circulating current while ensuring the quality of the current output.

If the reference voltage vector is located in other sectors or subregions, similar analyses can be performed according to the aforementioned principles, leading to the development of the corresponding improved switching sequences.However, these terms are not enumerated individually here.

3 Experimental verification

To validate the above analysis and test the effectiveness of the proposed novel switching sequence,an experimental hardware platform was developed.Table 2 lists the parameters of the experimental platform and Fig.6 shows photographs of the front and rear views.

The experimental waveforms using various sequence designs are depicted in Fig.7 for modulation ratios of 0.2, 0.4, 0.6, and 0.8.As observed from the simulated and experimental results, the use of the novel sequence design effectively suppressed the magnitude of the circulating currents.Furthermore, an analysis of the output current harmonics revealed that the novel switching sequence could still achieve an output current quality consistent with that of the traditional switching sequence, as illustrated by the current waveforms and THD data in Fig.7.

Fig.4 State assignment and circulating current diagram for sub-region 2 within sector I using the proposed novel switching sequences.

Fig.5 Diagram of circulating current for sub-region 9 of sector I.

Table 2 Experimental parameters.

ParameterValue V dc400 V V grid190 V C1,C2560 μF L1,L24 mH L 1 mH

Fig.6 Front and rear views of the experimental platform.

Fig.7 Experimental waveforms of the original and novel switching sequences.

The harmonics of the output voltage and current for both the original and novel switching sequences are summarized in Table 3.In fact, because circulating currents can cause some degree of output current distortion, the novel switching sequence also provides a certain degree of reduction in the output current harmonics.

Comparative results of the circulating current amplitudes at different modulation ratios when employing traditional interleaved paralleling and integrated paralleling with various sequence designs are shown in Fig.8.Compared with the interleaving method, the integrated modulation method significantly reduces the circulatingcurrent amplitude across all modulation indices, and the adoption of the improved switching sequence can further decrease the circulating current amplitude,with an average reduction of up to 32 %.

Table 3 Voltage and current THD for both switching sequences.

Modulation Index Original Switching SequenceProposed Switching Sequence Output VoltageOutput CurrentOutput VoltageOutput Current 0.239.36 %7.48 %39.21 %7.27 %0.419.37 %3.76 %19.04 %3.64 %0.612.29 %2.59 %12.22 %2.48 %0.88.59 %1.95 %8.57 %1.90 %

Fig.8 Comparison of circulating current for interleaving, integrated paralleling with various sequence designs.

According to the principles of space vector PWM, the output-side harmonics of the inverter are primarily determined by the base vectors used in the synthesis of the reference voltage vector.The novel sequence design does not alter the five-level basic vectors employed during modulation, thus ensuring that the output-side harmonics remain the same as those in the traditional sequence design.Concurrently, the state distribution of the novel switching sequence is flexible to ensure minimal circulating current throughout the modulation process.Simulation and experimental results confirmed the effectiveness of the proposed sequence design principles.

In general,the parallel operational modes of three-level converters can be categorized into three types: synchronous, interleaved, and integrated.A performance comparison of various methods is presented in Table 4,where the main comparison items include the AC-side harmonic distortion,circulating current magnitude,and circulating current suppression.

4 Conclusion

For high-power applications, there is often a need to increase the system capacity and reduce output harmonics.The integrated modulation with the new switching sequence proposed in this study can meet such demands.The new switching sequence does not alter the five-level base vectors used in the synthesis process of the reference voltage vector,thus maintaining the five-level output characteristics of the parallel three-level inverters and achieving better output current quality.However, in the process of allocating five-level switching states to parallel three-level inverters, the new switching sequence provides sufficient flexibility to effectively reduce the magnitude of the circulating current.

The innovative switching sequence proposed in this study performs better in terms of loop current magnitude and harmonic performance, as evidenced by the fact that its loop current is smaller in two consecutive switching cycles, and its harmonics are also smaller.The simulation results and experimental waveforms verified the accuracy of the relevant theory and conclusions, and the effect of the new state distribution on suppressing circulating currents and reducing harmonic distortion was also tested.As the most suitable method for comparison within the same category,the improved switching sequence proposed in this study was comprehensively compared with recently published literature [9].The data indicate that under various usage scenarios, that is, for different modulation indices, the method presented in this paper can significantly reduce the circulating current amplitude duringparallel inverter operation, with a maximum reduction of up to 44 % and an average reduction of 32 %.Concurrently, although the primary intention of the improved switching sequence proposed in this study was to reduce circulating currents, the harmonic content on the AC output side of the converter was also effectively reduced,with a maximum reduction of 4.5 % and an average reduction of 3.2 %.These data fully substantiate the feasibility and effectiveness of the proposed method.

Table 4 Performance comparison of various modulation methods.

Modulation MethodsHarmonic distortionCirculating current magnitudeCirculating current suppression Synchronous paralleling [5]HighLowEasy Interleaved paralleling [7]MediumHighHard Integrated modulation [9]LowMediumHard Proposed methodLowLowMedium

Regarding the scalability of the proposed method, it is applicable to inverters of any level, although the specific state allocation and switching sequence require corresponding analyses.However, if the number of inverters operating in parallel exceeds two, the design method proposed in this paper will face technical challenges;for example, the circulating current paths between multiple inverters are significantly complex, making it difficult to ensure that the circulating currents remain stable.Therefore, scalability issues require further in-depth research.

CRediT authorship contribution statement

Weiwei Li: Writing - original draft.Guoxiang Hua:Writing - review & editing, Visualization.Xing Huang:Supervision. Xueguang Zhang: Data curation.

Declaration of competing interest

The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

Acknowledgments

This work was supported by the National Natural Science Foundation of China (Grant No.51977046) and Wuxi University Research Start-up Fund for Introduced Talent (2022r021).