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Global Energy Interconnection
Volume 1, Issue 3, Aug 2018, Pages 319329
Systematic design method for PI controller with Virtual Resistorbased Active Damping of LCL filter
Keywords
Abstract
1 Introduction
Gridconnected converters (GcCs) constitute an indispensable intermediate between the power grid and distributed generation systems. To mitigate the switching harmonics produced by these converters, LCL filters are usually used. This is due to the fact that this type of filters offers high attenuation ability with reduced size and cost [13]. However, the LCL filter resonance may destabilize the closed loop control of the system [4]. To overcome this issue, several passive and active damping methods are suggested to enhance the stability of the system. Active damping methods (AD) are more adopted than passive damping ones (PD), since they ensure better damping without additional power loss and heat dissipation apparatus [57].
The Virtual Resistor based Active Damping (VRAD)combines the advantages of both PD and AD methods. In fact, it gives high damping performances as the real resistorbased passive damping RRPD, while avoiding supplementary power loss and encumbrance [8,9]. In addition, compared to other AD methods, the VRAD is characterized by its robustness, simple implementation and high efficiency [10,11].Nevertheless, the VRAD features may be affected in digitally controlled systems due to the time associated delay [12,13].In fact this digital time delay can change the impedance characteristics of the VRAD and reduces the system phase margin, resulting in poor robustness, especially in low switching frequencies [14,15]. This time delay is indispensible in digitally controlled systems since it incorporates the computation and the PWM delays.
Another key factor that affects the system stability is the large grid impedance variation Lg [1618]. In fact, in weak grids, the Lg values can vary significantly due to low power capacity transformers, parallel connections of GcCs and long distribution wires [18,19]. The goal of this paper is to suggest a systematic, robust and optimized design procedure for the VOC with VRAD for LCLGcC. Compared to previous associated works [1926], the suggested design procedure takes into account the following restrictions that may threaten the stability of the system: 1) time delay of digital controllers, 2) filter parameters changes and 3)large grid inductance variations. Although under the above mentioned restrictions, the suggested design procedure ensures the following performances: 1) sufficient phase margins and gain margins, 2) the minimized grid current THD value and 3) the minimized steadystate error.
This paper is organized as follows. Firstly, in section II, the VOC with VRAD for LCLGcC is presented. After that, in section III, the controllers design procedure of the VOC with VRAD is detailed and discussed. After that, in section IV, simulation results obtained via MatlabSimulink are presented. Finally, section V is devoted to experimental tests. The obtained experimental results prove robustness and effectiveness of the suggested design procedure.
2 VOC with VRAD for LCLGcC
The LCLGcC power circuit and the VOC with VRAD are presented by Fig.1 (a) and Fig.1 (b), respectively. As depicted in Fig.1 (b), the control strategy is composed of several modules which are:
 DClink voltage control module: This module controls the DClink voltage Vdc via a PI controller. It generates the reference current from the difference between reference DClink voltageand the measured one Vdc.
 Grid synchronization module: The aim of this module is to compute the position of the grid voltage vector θdq.This position is used in the abctodq and dqtoabc coordinate transformations.
 Grid currents regulation module: This module is based on a PI controller and in the dq reference frame. It controls the gridside currents. The daxis grid current referenceis determined by the DClink voltage control module. The qaxis grid current is imposed equal to zero to ensure a unit power factor operation.
VRAD module: This module is based on a virtual resistor used to actively reduce the resonance of the LCL filter. This virtual resistor is equivalent to a real damping resistor placed in series with the filter capacitor. Compared to the RRPD, the VRAD ensures better current harmonic attenuation without extra power loss and encumbrance.
 PWM module: The Pulse Width Modulation module determines the power converter switching states during the kth sampling period.
Fig.1 (a) LCLGcC (b) VOC with VRAD
Fig.2 shows the timing diagram of the implemented VOC with VRAD that presents the PWM references sampling and update instants and the execution time of the different aforementioned modules. As shown in this figure,the input variables Vdc, Vg(a,b,c), i2(a,b,c) and ic(a,b,c) are sampled at higher carrier vertexes, while the converter voltage vector is updated. Consequently, the time delay is equal to the sampling period Ts. In Fig.2, tPI_Vdc, tθdq, tPI_i2, tVRAD and tPWM are the execution time of the respective modules:DClink voltage control module, grid synchronization module, grid currents regulation module, VRAD module and PWM module. Table 1 shows the system and LCL filter parameters. Also, tAD and Tex are, respectively, the A/D conversion time and the execution time.
Fig.2 PWM references sampling and update instants
Table 1 Parameters of the system
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3 Control parameters tuning
Fig.3 Controllers parameters design algorithm
Fig.3 presents the diagram that gives the different steps of the proposed controllers parameters tuning method.As shown in this figure, in the first step are defined the constraints and the desired performances. These constraints are: 1) LCL filter parameters uncertainties, overestimated to ±20%; 2) time delay related to digital controllers and 3)large grid impedance variation, overestimated to 13 mH.While the desired performances are: 1) reduced steadystate error (EA < 5%); 2) sufficient gain margin (Gm < 9 dB);3) sufficient phase margin (45°< Pm <65°) and 4) reduced grid current THD (THDi2 < 5%). The next step consists in computing the integral gain Ki according to the requirement on the steady state error. After that, the virtual resistor Kr is computed considering a well damped RRPD. Afterward,in the fourth step, the proportional gain Kp is deduced from the region where the desired restrictions on Gm and Pm are ensured. Then, in the fifth step, the designer should verify that the obtained controllers parameters ensure a grid current THD less than 5% according to the IEEE 5191992 standard. If this is not the case, the designer should increase the value of the virtual resistor Kr. In the sixth step,the designer should verify that, for the obtained controllers parameters, the desired performances are ensured even for LCL filter parameters uncertainties. If this is not the case,the designer should increase the value of the Kp, while ensuring the desired restrictions on Gm and Pm. Finally, in the last step, are presented the final controllers parameters that ensure the desired performances even under the constraints defined in the first step. The different steps of the controllers design method are presented and detailed in the following paragraphs.
3.1 Tuning of Ki
Since the delay caused by the PWM process is negligible with regard to the dynamic of the coupling terms ±ωgL2 gi2dq and since the value of these terms can be assumed constant between two consecutive periods,Fig.1(b) can be simplified as in Fig.4(a) [8,26]. This figure gives the simplified discrete zdomain dqaxis block diagram of the VOC with VRAD. In this figure, KPWM is the PWM converter gain and esTs is the computation delay.Gr and Hr are the transfer functions from i2dq to Vidq and from icdq to Vidq, respectively. Gr and Hr are expressed by equations (1) and (2), respectively.
According to (1), (2) and Fig.4 (a), the transfer function GADr is expressed by (3).
According to Fig.4 (a) and (3), the system open loop transfer function is given by (4).
The control strategy employed for controlling the gridside currents is based on a VOC designed in the dq reference frame. For that case, the controlled i2dq currents are continuous signals during steady state operation. Thus,during steady state operation, the use of PI controllers will lead to an amplitude error equal to zero. As regards the phase error, we firstly notice that the grid voltage phase θdq is determined with good accuracy using wellknown grid synchronization techniques. As a result, the phase error is zero during steady state operation thanks to the use of the abctodq and dqtoabc coordinate transformations.However, during transient states caused, for example, by random swings of the active (or reactive) power drawn by the LCLGcCs, the i2dq currents are timevarying, which will result in amplitude and phase errors. However, given that the proposed design method ensures the achievement of a high bandwidth control, the amplitude and phase error will be very low during the transient state operation. Since the grid voltage phase is determined with good accuracy,only the amplitude error EA will be considered in this paper and it is expressed by equation (6) [28]. In equation (6),Tfo denotes the system open loop transfer function gain at the fundamental frequency fo. Since the simplified transfer function of the PI controller (5) for fundamental frequency fo is given by (7), and based on (4), neglecting the influence of the filter capacitor at fo, Tfo is given by (8).
According to (8), EA depends on the integral gain Ki.Consequently, the choice of Ki depends on the restrictions of steadystate error. For an EA less than 5%, Tfo should be larger than 26dB. Therefore, in order to ensure EA less than 5% even for large grid impedance variation, Ki must satisfy equation (9). A value of 40000 is selected for Ki.
Fig.4 (a) Block diagram of the system with VRAD in the dq reference frame (b) Simplified equivalent block diagram
3.2 Tuning of Kr
The virtual resistor Kr is selected according to a well damped RRPD. Thus, the choice of the real resistor value is an important step. This choice should be a compromise between low power loss and sufficient stability margins.The real damping resistor is computed based on the following equation. [29]
The real resistor Rd produces power loss Pd expressed by (11), where iin and i2n denote the nth harmonic order of the inverter and grid current, respectively. The obtained power loss associated to Rd is equal to 4.5W which represents 0.1%of the rated active power P.
Fig.5 reports the root locus of the T transfer function when Rd varies from 0 to 30 Ω. According to this figure, the system stability is improved as Rd rises. However, the rise of Rd will produce higher Pd. According to Fig.5, for Rd=6Ω(the computed value), the obtained gain margin Gm is equal to 47° and the obtained phase margins Pm is equal to 9.12 dB, while the obtained power loss Pd represents only 0.1% of P. Consequently, the obtained damping resistor(Rd=6Ω) is a good compromise between power loss and stability. Fig.6 (a) presents the single phase representation of an undamped LCL filter in high frequencies. According to the power circuit given by Fig.6 (a), F1 from Vco to Vi is expressed by (12.a), whereas, that from ic to Vco is expressed by (12.b). Based on (12.a) and (12.b), the block diagram of the undamped high frequency LCL filter can be deduced as is Fig.6 (c). Based on this diagram and Fig.4, the VRAD can be simplified as in Fig.6 (d). According to the obtained modified system given, the transfer function H from Vco to Vi is expressed by (12.c). On the other hand,based on Fig.6 (b), which presents the single phase representation of an LCL filter damped with a real resistor Rd in high frequencies, the transfer function G from VcR to Vi is expressed by (12.d). To ensure that the system with VRAD has the same poles as the system with RRPD, the denominators of F and G should be equal. Consequently,the virtual resistor Kr value is selected based on (12.e),and Kr is equal to 18 since the correspondent Rd is equal to 6Ω.
Fig.5 Closedloop system Root locus for Rd includes in [0 30Ω]
Fig.6 (a) High frequency single phase circuit of an undamped LCL filter(b) High frequency single phase circuit of an LCL filter damped with a real resistor Rd(c) LCL filter block diagram (d) Modified control structure
3.3 Tuning of Kp
The choice of Kp is based on the requirements on the gain and phase margins Gm and Pm. Since the phase plot will cross over 180° only once at fres, Gm is given by the following equation:
Substituting (5) into (4) and according to (13), Gm is given by the following equation:
Since Gm should be greater than 9dB although large grid impedance changes and according to (14), Kp must verify condition (15). For Ki equals to 40000, Kr equals to 18 and Lg varies up to 13mH, Kp must be less than 4.8 as shown in (15).
The selection of Kp can be refined by the requirement of Pm which is expressed as in (16). Based on (16), (4) and (5),the expression of Pm is given by (17).
where fc is the crossover frequency. Since the influence of the filter capacitor can be ignored for frequencies up to fc and according to (4), the gain of T(s) at fc is expressed by(18). In addition, the PI controller can be simplified to Kp at fc as given in (19). Since T(s) is unity at fc and substituting(19) into (18), fc is given by equation (20).
Finally, the Pm of the system is expressed as follows
Fig.7 shows the phase margin Pm (equation (21)) with regard to Lg variations for Kp included in [0, 4.8] (value that ensures a gain margin greater than 9 dB (condition given by (15)). According to Fig.7, when Lg rises, Pm is degraded for several values of Kp. The variation interval that ensures simultaneously a 45°<Pm<65° and a Gm>9 dB is [1.8, 3.2].A value of 2.5 is selected for Kp.
Fig.7 Phase margin Pm according to grid impedance
3.4 Requirement on the grid current THD
Fig.8 shows the grid current THDi2 for different values of Lg and Kr. It can be noted, according to this figure, that when Kr and Lg rise, the grid current decreases. In this step, the designer verifies that for the obtained controllers parameters,the obtained THDi2 is well below 5%. If this is not the case,the value of the virtual resistor Kr should be increased. As shown in Fig.8, for the obtained controllers parameters, the THDi2 is equal to 1.2% and 0.7% for Lg equals to 0mH and 13mH, respectively.
Fig.8 Grid current THD according virtual resistor and grid inductor
3.5 Robustness against filter parameters change
In this step, the designer verifies that the selected control parameters values ensure robust stability of the system despite filter parameters change. In order to verify this condition, the Bode diagrams of T(s) are plotted taking into account the Lg changes and the filter parameters uncertainties. In Fig.9, C varies from 1.6 μF to 2.4 μF (2 μF±20%), in Fig.10, Li varies from 4 mH to 6 mH (5 mH±20%) and in Fig.11, L2 varies from 1.6 mH to 2.4 mH (2 mH±20%). In these figures, Lg is set to 13 mH.According to these figures, Gm is greater than 15.8 dB and Pm is greater than 37.8° for all the cited cases. In addition,Tfo is greater than 31.3 dB, which corresponds to an EA equal to 0.85.
Fig.9 Bode diagrams of the open loop system for Lg equal to 13 mH, C varies from 1.6 μF to 2.4 μF (2 μF±20%)
Fig.10 Bode diagrams of the open loop system for Lg equal to 13 mH, Li varies from 4 mH to 6 mH (5 mH±20%)
Fig.11 Bode diagrams of the open loop system for Lg equal to 13 mH, L2 varies from 1.6 mH to 2.4 mH (2 mH±20%)
4 Simulation results
Table 2 presents the controllers parameters obtained based on the suggested design procedure as well as the obtained performances for Lg=0 and Lg=13 mH. As depicted on this table, the desired requirements on EA,fc, Pm and Gm are achieved even for huge changes on Lg.During simulation tests under MatlabSimulink, the fsω is equal to 10 kHz. Fig.12 presents the response of the dclink voltage Vdc. As shown in this figure, Vdc is well regulated during steady state operation since it reaches its reference which is equal to 150 V. Fig.13 presents the waveforms of the grid current and voltage (i2a and Vga)during steady state operation. This figure shows that a unit power factor operation is ensured. Fig.14 presents the waveform of the grid current i2a for Lg equal to zero. The obtained simulated grid current i2a and its reference valueare equal to 1.218A and 1.22A, respectively. Thus,the obtained EA is equal to 0.12%. Moreover, it should be noticed that, the obtained grid current THD is equal to only 1.2%. The obtained EA and THD value show the high quality of the grid current. Supplementary inductors of 13 mH are placed in series with L2 to prove the robustness of the VRAD. As depicted in Fig.14, the system stability is ensured even for weak grid conditions. In addition, for Lg equal to 13 mH, the THD value of the simulated grid current is equal to 0.7%. It can be noted according to the obtained simulation results that the implemented VRAD is robust and thus the proposed controllers design procedure is efficient.
Table 2 Controller Parameters
Parameter Value Kp 2.5 Ki 40000 Kr 18 Lg Lg=0 mH Lg=13 mH Constraints Pm 64.1° 47.3° 45°<Pm<65°Gm 23.5 dB 19.4 dB Gm>9 dBTfo 57.89 dB 26.5 dB Tfo>26 dB EA 0.12% 4.7% EA<5%THD(i2) 1.2% 0.7% THD(i2)<5%Controller Performances
Fig.12 Vdc response for Lg=0 mH
Fig.13 i2a and Vg waveforms for Lg=0 mH
Fig.14 i2a waveform during steadystate for Lg=0 mH
Fig.15 i2a waveform during steadystate for Lg=13 mH
Fig.16 Experimental setup
5 Experimental results
Fig.16 shows the experimental setup used to test the VRAD in order to prove efficiency, robustness as well as performances of the controllers design procedure. This experimental setup incorporates two main parts: The first one consists in a power part that contains: 1) the grid utility source, 2) an autotransformer to vary grid voltage magnitude, 3) A DClink capacitor (1100 μF/800 V), 4) a variable resistive load connected to the DClink capacitor, 5) a 20 kVA three phase high voltage power converter, 6) an LCL filter (three inductors (5 mH/10 A), three capacitors(2 μF/400 V) and three inductors (2 mH/10 A)) and 7)three inductors (4.5 mH/10 A) used to emulate the huge variations of Lg. While the second one consists in a control part that includes: 1) the STM32F4Discovery,2) a measurement board, 3) an interface board used to adjust the voltage level between the converter drivers, and 4) the Host PC used in order to configure the STM32F4Discovery.
The switching frequency and the DClink reference voltage fixed to 10 kHz and 150 V, respectively,during experimental tests. As presented in Fig.16, a supplementary inductance of 4.5 mH was inserted in series with Lin addition to the real inductancethat 2 contains the inductance of the autotransformer (used during experimental tests) and that of distribution wires.Fig.17 gives the Vdc and i2a waveforms after applying the switching states. It can be shown that the Vdc voltage becomes equal to its reference during steady state. Fig.18 presents the waveforms of Vga and i2a during steady state.According to this figure, Vga and i2a are in phase and therefore a unit power factor operation is attained. Fig.19 gives the waveform of the measured i2a obtained after the application of the switching state for Lg=. The obtained measured grid current i2a and its reference value are equal to 1.17A and 1.21A, respectively. Thus, EA is equal to 2.6%. The grid current THD value is equal to 2.9%which satisfies grid code requirements. Fig.20 presents the steady state response of the measured i2a for Lg= +.As depicted in this figure, the system remains stable even for huge variation of Lg. The obtained experimental results are similar to those achieved in simulation by MatlabSimulink software tool. Moreover, they prove the high performance, robustness and efficiency of the VRAD and consequently the reliability as well as efficiency of the suggested controllers design procedure.
Fig.17 Response of V and i for L=dc2ag
Fig.18 Vga and i2a waveforms for Lg=
Fig.20 Measured grid current i2a (1 A/div) for Lg= +
Fig.19 Measured grid current i (1 A/div) for L=2ag
6 Conclusion
VRAD is an efficient solution to mitigate the LCL filter resonance. Nevertheless, filter parameters uncertainties,large grid impedance variation as well as time delay related to digital controllers can significantly endanger the system in terms of stability. To overcome these issues, this paper suggests a systematic and robust procedure for VOC with VRAD for LCLGcC that ensures although under the aforementioned restrictions: 1) a sufficient Pm and Gm, 2) a vlow grid current THD value and, 3) a reduced steadystate error EA. Both simulation and experimental results have demonstrated that, based on the proposed tuning procedure,the LCLGcC can achieve high steadystate performances,high quality of grid current as well as robust stability margins.
Acknowledgements
This work was supported by the Tunisian Ministry of High Education and Research under Grant LSEENITLR11ES15.
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Fund Information
supported by the Tunisian Ministry of High Education and Research under Grant LSEENITLR11ES15；
supported by the Tunisian Ministry of High Education and Research under Grant LSEENITLR11ES15；